HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping

• Published in: 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines pp. 117 - 124
• Main Authors: Lavin, C, Padilla, M, Lamprecht, J, Lundrigan, P, Nelson, B, Hutchings, B
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2011
• Subjects: Acceleration; Algorithm design and analysis; Design automation; Field programmable gate arrays; FPGA; Generators; HMFlow; Open Source; Rapid Prototyping; RapidSmith; Routing; Software; XDL; Xilinx
• ISBN: 9781612842776; 1612842771
• DOI: 10.1109/FCCM.2011.17

The FPGA compilation process (synthesis, map, place, and route) is a time consuming task that severely limits designer productivity. Compilation time can be reduced by saving implementation data in the form of hard macros. Hard macros consist of previously synthesized, placed and routed circuits that enable rapid design assembly because of the native FPGA circuitry (primitives and nets)which they encapsulate. This work presents results from creating a new FPGA design flow based on hard macros called HMF low. HMF low has shown speedups of 10-50X over the fastest configuration of the Xilinx tools. Designed for rapid prototyping, HMF low achieves these speedups by only utilizing up to 50 percent of the resources on an FPGA and produces implementations that run 2-4X slower than those produced by Xilinx. These speedups are obtained on a wide range of benchmark designs with some exceeding 18,000 slices on a Virtex 4 LX200.