Technology and design aspects of ultra-thin silicon chips for bendable electronics - Richter, H.; Rempp, H.D.; Hassan, M.-U.; Harendt, C.; Wacker, N.; Zimmermann, M.; Burghartz, J.N. (2009 IEEE International Conference on IC Design and Technology, 2009)
Plastic electronics, thin-film-transistors on foil and ultra-thin chips on foil are technologies currently pursued to support the strongly emerging market for flexible electronics. Ultra-thin CMOS chips in such systems will provide solutions whenever high circuit performance and/or complexity are required. Ultra-thin Si chips (6 to 20 mum) are fabricated by using a recently introduced technology based on the pre/post-process modules Chipfilm TM and PickCrack&Place TM combined with a standard CMOS process. Prior to CMOS processing 200 nm cavities are formed beneath the chip surface. The silicon quality is very comparable to that of bulk control wafers leading to similar process parameters and parameter variations. Fully operational digital and mixed-signal circuits having 30 k and 38 k/2.7k digital/analog CMOS transistors, respectively, are built on ultra-thin silicon chips by using an in-house CMOS gate array technology. The issue of piezoresistive effects in MOS transistors is studied on test transistors and small test circuits, where mechanical stress was introduced by bending a system of chip mounted on 50-mum Kapton foil. The results are compared to bulk silicon measurements. In addition, effects to circuit design, particularly on parametric yield, are deduced. The Chipfilm TM technology not only offers ultra-thin CMOS chips for electronic foil systems but can also be exploited for 3D circuit integration.