Process variability at the 65nm node and beyond - Nassif, S.R. (2008 IEEE Custom Integrated Circuits Conference, 2008)
The impact of manufacturing-induced variations has been well established as a first order impediment to modern integrated circuit design [1]. Numerous research efforts are currently underway to (a) understand and characterize variability[2], to (b) predict its impact on circuit behavior[3], and (c) to develop layout and circuit design techniques to reduce the impact of variability[4]. Simultaneously, except for the most advanced high performance designs, the increasing cost of migrating to sub-65 nm technology nodes is slowing down adoption of advanced technologies. This slow down is allowing current efforts to catch up and help mitigate variability as an impediment.