Process variability at the 65nm node and beyond

The impact of manufacturing-induced variations has been well established as a first order impediment to modern integrated circuit design [1]. Numerous research efforts are currently underway to (a) understand and characterize variability[2], to (b) predict its impact on circuit behavior[3], and (c)...

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Published in2008 IEEE Custom Integrated Circuits Conference pp. 1 - 8
Main Author Nassif, S.R.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2008
Subjects
CMOS technology
Costs
Impedance
Integrated circuit interconnections
Investments
Laboratories
Manufacturing processes
MOSFET circuits
Switches
USA Councils
Online AccessGet full text
ISBN9781424420186
1424420180
ISSN0886-5930
DOI10.1109/CICC.2008.4672005

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Abstract The impact of manufacturing-induced variations has been well established as a first order impediment to modern integrated circuit design [1]. Numerous research efforts are currently underway to (a) understand and characterize variability[2], to (b) predict its impact on circuit behavior[3], and (c) to develop layout and circuit design techniques to reduce the impact of variability[4]. Simultaneously, except for the most advanced high performance designs, the increasing cost of migrating to sub-65 nm technology nodes is slowing down adoption of advanced technologies. This slow down is allowing current efforts to catch up and help mitigate variability as an impediment.
AbstractList The impact of manufacturing-induced variations has been well established as a first order impediment to modern integrated circuit design [1]. Numerous research efforts are currently underway to (a) understand and characterize variability[2], to (b) predict its impact on circuit behavior[3], and (c) to develop layout and circuit design techniques to reduce the impact of variability[4]. Simultaneously, except for the most advanced high performance designs, the increasing cost of migrating to sub-65 nm technology nodes is slowing down adoption of advanced technologies. This slow down is allowing current efforts to catch up and help mitigate variability as an impediment.
Author Nassif, S.R.
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Snippet The impact of manufacturing-induced variations has been well established as a first order impediment to modern integrated circuit design [1]. Numerous research...
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StartPage 1
SubjectTerms CMOS technology
Costs
Impedance
Integrated circuit interconnections
Investments
Laboratories
Manufacturing processes
MOSFET circuits
Switches
USA Councils
Title Process variability at the 65nm node and beyond
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