Networks-on-chip topology optimization subject to power, delay, and reliability constraints

In this paper, we present a novel approach in Networks-on-Chip topology optimization, by considering the network power consumption, packet transmission delay, and system reliability, simultaneously. We use the Particle Swarm Optimization technique to acquire the most suitable topology architecture,...

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Bibliographic Details
Published in2010 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 2354 - 2357
Main Authors Elmiligi, H, Morgan, A A, El-Kharashi, M W, Gebali, F
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2010
Subjects
Binary trees
Constraint optimization
Delay
Energy consumption
Network topology
Network-on-a-chip
Particle swarm optimization
Power system reliability
Telecommunication traffic
Voltage
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ISBN1424453089
9781424453085
ISSN0271-4302
DOI10.1109/ISCAS.2010.5537194

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Summary:In this paper, we present a novel approach in Networks-on-Chip topology optimization, by considering the network power consumption, packet transmission delay, and system reliability, simultaneously. We use the Particle Swarm Optimization technique to acquire the most suitable topology architecture, which achieves maximum reliability as well as minimum delay and power consumption. The optimization problem, which considers six design variables: network topology architecture, traffic distribution, processing elements' mapping, noise power, voltage swing, and probability of edge failure, is validated through a case study of an H.263-encoder MP3-decoder.
ISBN:1424453089
9781424453085
ISSN:0271-4302
DOI:10.1109/ISCAS.2010.5537194