High-order multi-bit incremental converter with Smart-DEM algorithm

• Published in: 2013 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 157 - 160
• Main Authors: Yao Liu, Bonizzoni, Edoardo, Maloberti, Franco
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2013
• Subjects: Algorithm design and analysis; Clocks; Guidelines; Linearity; Modulation; Sigma-delta modulation; Signal resolution
• ISBN: 9781467357609; 146735760X
• ISSN: 0271-4302
• DOI: 10.1109/ISCAS.2013.6571806

This paper describes the design method for highorder multi-bit incremental converters aiming at high resolution (> 14 bits) with Smart-DEM algorithm. Traditional 2 nd and 3 rd -order incremental ADCs use 1-bit quantizer. These structures lead to long conversion time for each sample to achieve the expected resolution and high power consumption due to the large output swing of the op-amps. Also, the fractional coefficients along the accumulation path that avoid instability degrade the performance. On the contrary, modulators employing multi-bit quantizer and DAC do not suffer from these problems. Although the mismatch of unity elements in the DAC causes non-linearity issue, this can be suppressed by Smart-DEM algorithm. Because the Smart-DEM algorithm is quite compact and easy to implement, the modulator benefits extra bits performance directly from the multi-bit DAC with affordable digital circuits overhead. In this paper several structures for incremental ADCs utilizing multi-bit quantizer are presented. The positive-and-negative DAC and the Smart-DEM algorithm are explained. With 3-bit quantizer, the simulation results show that the 2 nd -order incremental ADC obtains 18-bit resolution with 256 clock periods.