A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration - Terada, Kotaro; Yanagisawa, Masao; Togawa, Nozomu (APCCAS : 2014 IEEE Asia Pacific Conference on Circuits and Systems : 17-20 November 2014, 2014)
Keywords: Clocks; Computer architecture; Data transfer; Delays; Image edge detection; Integrated circuit interconnections; Registers