A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration

• Published in: APCCAS : 2014 IEEE Asia Pacific Conference on Circuits and Systems : 17-20 November 2014 pp. 248 - 251
• Main Authors: Terada, Kotaro, Yanagisawa, Masao, Togawa, Nozomu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2014
• Subjects: Clocks; Computer architecture; Data transfer; Delays; Image edge detection; Integrated circuit interconnections; Registers
• DOI: 10.1109/APCCAS.2014.7032766

In deep-submicron era, interconnection delays are not negligible even in high-level synthesis and RDR (Regular-Distributed-Register) architecture has been proposed to cope with this problem. In this paper, we propose a high-level synthesis algorithm using operation chainings which reduces the overall latency targeting RDR architectures. Our algorithm consists of three steps: The first step enumerates candidates for chaining. The second step introduces maximal chaining distance (MCD), which gives the maximum allowable distance on RDR architecture between chaining candidate operations. The last step performs list-scheduling and binding simultaneously using the results of two preceding steps. Our algorithm enumerates feasible chaining candidates and selects the best ones for RDR architecture. Experimental results show that our algorithm reduces the latency by up to 28.6%, the number of registers by up to 37.5%, the number of multiplexers by up to 25.0%, compared to the conventional approaches.