APA (7th ed.) Citation

Terada, K., Yanagisawa, M., & Togawa, N. (2014, November). A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration. APCCAS : 2014 IEEE Asia Pacific Conference on Circuits and Systems : 17-20 November 2014, 248-251. https://doi.org/10.1109/APCCAS.2014.7032766

Chicago Style (17th ed.) Citation

Terada, Kotaro, Masao Yanagisawa, and Nozomu Togawa. "A Floorplan-driven High-level Synthesis Algorithm with Operation Chainings Using Chaining Enumeration." APCCAS : 2014 IEEE Asia Pacific Conference on Circuits and Systems : 17-20 November 2014 Nov. 2014: 248-251. https://doi.org/10.1109/APCCAS.2014.7032766.

MLA (9th ed.) Citation

Terada, Kotaro, et al. "A Floorplan-driven High-level Synthesis Algorithm with Operation Chainings Using Chaining Enumeration." APCCAS : 2014 IEEE Asia Pacific Conference on Circuits and Systems : 17-20 November 2014, Nov. 2014, pp. 248-251, https://doi.org/10.1109/APCCAS.2014.7032766.