An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors

• Published in: 2007 IEEE 13th International Symposium on High Performance Computer Architecture pp. 2 - 12
• Main Authors: Dybdahl, H., Stenstrom, P.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2007
• Subjects: Bandwidth; Degradation; Delay; Microprocessors; Pollution; Size control
• ISBN: 9781424408047; 1424408040
• ISSN: 1530-0897
• DOI: 10.1109/HPCA.2007.346180

The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the capacity of shared last-level caches efficiently and to allow for a short access time, proposed non-uniform cache architectures (NUCAs) are organized into per-core partitions. If a core runs out of cache space, blocks are typically relocated to nearby partitions, thus managing the cache as a shared cache. This uncontrolled sharing of all resources may unfortunately result in pollution that degrades performance. We propose a novel non-uniform cache architecture in which the amount of cache space that can be shared among the cores is controlled dynamically. The adaptive scheme estimates, continuously, the effect of increasing/decreasing the shared partition size on the overall performance. We show that our scheme outperforms a private and shared cache organization as well as a hybrid NUCA organization in which blocks in a local partition can spill over to neighbor core partitions