Design of high-rate long-length structured QC-LDPC with good error performance

In order to improve error performance of data storage, this paper presents a code-design algorithm for a class of structured quasi-cyclic low-density parity-check (SQC-LDPC) codes with high rate ( R >;= 0.9 ) and long-length (10 4 <; 60 n). In the design of parity-check matrix, optimized degre...

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Published in2011 5th International Conference on Signal Processing and Communication Systems pp. 1 - 4
Main Authors Xiong Yin, Zhaoxia Zheng, Yi Dan, Zhenglin Liu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2011
Subjects
ACE
Algorithm design and analysis
Cost function
Encoding
error floor
Filling
Floors
high-rate
long-length
Parity check codes
Simulation
SQC-LDPC
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ISBN1457711796
9781457711794
DOI10.1109/ICSPCS.2011.6140871

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Abstract In order to improve error performance of data storage, this paper presents a code-design algorithm for a class of structured quasi-cyclic low-density parity-check (SQC-LDPC) codes with high rate ( R >;= 0.9 ) and long-length (10 4 <; 60 n). In the design of parity-check matrix, optimized degree distribution pairs are obtained based on the combination of density evolution and differential evolution with a modified cost function. Moreover, both fewer short block-cycles and larger approximated cycle extrinsic message degree (ACE) are also considered. Simulation results indicate that codes in this design method its simulation curve is close to Shannon limit and have lower error floor.
AbstractList In order to improve error performance of data storage, this paper presents a code-design algorithm for a class of structured quasi-cyclic low-density parity-check (SQC-LDPC) codes with high rate ( R >;= 0.9 ) and long-length (10 4 <; 60 n). In the design of parity-check matrix, optimized degree distribution pairs are obtained based on the combination of density evolution and differential evolution with a modified cost function. Moreover, both fewer short block-cycles and larger approximated cycle extrinsic message degree (ACE) are also considered. Simulation results indicate that codes in this design method its simulation curve is close to Shannon limit and have lower error floor.
Author Xiong Yin
Zhaoxia Zheng
Zhenglin Liu
Yi Dan
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  surname: Zhaoxia Zheng
  fullname: Zhaoxia Zheng
  email: zxzheng@mail.hust.com.cn
  organization: Dept. of Electron. Sci. & Technol., HuaZhong Univ. of Sci. & Technol., Wuhan, China
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  surname: Yi Dan
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  organization: Dept. of Electron. Sci. & Technol., HuaZhong Univ. of Sci. & Technol., Wuhan, China
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  surname: Zhenglin Liu
  fullname: Zhenglin Liu
  organization: Dept. of Electron. Sci. & Technol., HuaZhong Univ. of Sci. & Technol., Wuhan, China
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Snippet In order to improve error performance of data storage, this paper presents a code-design algorithm for a class of structured quasi-cyclic low-density...
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SubjectTerms ACE
Algorithm design and analysis
Cost function
Encoding
error floor
Filling
Floors
high-rate
long-length
Parity check codes
Simulation
SQC-LDPC
Title Design of high-rate long-length structured QC-LDPC with good error performance
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