Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs

• Published in: 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines pp. 125 - 132
• Main Authors: Korf, S, Cozzi, D, Koester, M, Hagemeyer, J, Porrmann, M, Ruckert, U, Santambrogio, M D
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2011
• Subjects: Design Automation; DH-HEMTs; Field programmable gate arrays; Homogeneous Hard Macros; Reconfigurable Computing; Registers; Routing; Table lookup; Wires
• ISBN: 9781612842776; 1612842771
• DOI: 10.1109/FCCM.2011.36

The regularity of resources found in FPGAs is a unique feature, which can be utilized in a number of applications, e.g., in timing critical applications or applications with a demand for homogeneous routing. Current synthesis tools do not support an automatic generation of homogeneous FPGA designs, such that a time-consuming hand-crafted design is required. We present a tool flow, which automatically generates homogeneous hard macros for Xilinx FPGAs starting from a high-level description, such as VHDL. Key functionalities of the tool flow are a homogeneous placer and a suitable routing algorithm, which aim at maintaining the homogeneity of the resulting hard macro. The place and route tools use a resource library that is automatically generated for the target FPGA family by extracting relevant information from the vendor tools. The tool chain is demonstrated for the design of hard macros for a time-to-digital converter and a tiled partially reconfigurable region. The resulting designs are evaluated with respect to resource requirements and timing constraints.