A sub-word-parallel Galois field multiply-accumulate unit for digital signal processors

• Published in: 2005 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1626 - 1629 Vol. 2
• Main Author: Roy, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Concurrent computing; Cyclic redundancy check; Delay; Digital signal processing; Digital signal processors; Error correction codes; Galois fields; Hardware; Reed-Solomon codes; Signal processing algorithms
• ISBN: 9780780388345; 0780388348
• ISSN: 0271-4302
• DOI: 10.1109/ISCAS.2005.1464915

This paper presents a versatile Galois field multiply-accumulate (MAC) unit, which is used as a compute block in a digital signal processor (DSP). The MAC unit can be used to perform error detection through parallel computation of cyclic redundancy checks (CRC). We propose a Galois field MAC based algorithm to perform parallel computation of m-bit CRC using i bits of the message at a time, where i /spl les/ m. Handling less than m bits in parallel enables a trade-off by significantly reducing the hardware area and delay of the compute block. The MAC can also be used to perform error correction employing Reed Solomon codes. It uses a sub-word-parallel architecture to optimise the performance of the proposed CRC algorithm and Reed Solomon encoding/decoding. Thus it enables programmable solution to a large variety of applications employing error control coding techniques in the communications and consumer electronics field.