A programmable clock generator HDL softcore

This paper presents a hardware implementation of a fully synthesizable, technology independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done...

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Bibliographic Details
Published in2007 50th Midwest Symposium on Circuits and Systems pp. 1 - 4
Main Authors Eisenreich, H., Mayr, C., Henker, S., Wickert, M., Schuffny, R.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.08.2007
Subjects
Clocks
Digital control
Digital-controlled oscillators
Frequency control
Hardware design languages
Jitter
Manufacturing
Robust control
Signal resolution
Testing
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ISBN1424411750
9781424411757
ISSN1548-3746
DOI10.1109/MWSCAS.2007.4488528

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Summary:This paper presents a hardware implementation of a fully synthesizable, technology independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a defined lock-in time of at most 8 reference cycles. ASICs in CMOS AMS 0,35 um and UMC 0,13 um have been manufactured and tested. Measurements show competitive results to state-of-the- art mixed signal implementations.
ISBN:1424411750
9781424411757
ISSN:1548-3746
DOI:10.1109/MWSCAS.2007.4488528