Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement

• Published in: 2008 IEEE Custom Integrated Circuits Conference pp. 193 - 196
• Main Authors: Jing Li, Haixin Liu, Salahuddin, S., Roy, K.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2008
• Subjects: Circuit simulation; Circuit stability; Circuit synthesis; Electrodes; Green's function methods; Magnetic tunneling; Random access memory; Read-write memory; Robust stability; Scalability
• ISBN: 9781424420186; 1424420180
• ISSN: 0886-5930
• DOI: 10.1109/CICC.2008.4672056

Spin-Torque Transfer Magnetic RAM (STT MRAM) has emerged as a promising candidate for future universal memory. It not only combines the desirable attributes of all current memory technologies (SRAM, DRAM and flash memories) but also solves the critical drawbacks of conventional MRAM technology: poor scalability and high write current. However, variations in process parameters can lead to large number of cells to fail, severely affecting the yield of the memory array. In this paper, we provide a thorough understanding of the interrelationship between design parameters and parametric failures of STT MRAM cell in presence of process variations. Based on comprehensive physics-based model, solving the Non-Equilibrium Greenpsilas Function (NEGF) formalism in the ballistic regime, we develop an optimization methodology for robust cell design (in 1T1M configuration) to account for both stability and cell area. Further, we propose an efficient circuit design for variation tolerance. The proposed technique can effectively decouple the conflicting design requirements of read/write stability and area in conventional 1T1M cell, leading to considerably improved yield of memory array. Simulation results show that in our proposed cell, the robustness (cell stability) is improved by 36% with only 9% area overhead.