FUSE: Front-End User Framework for O/S Abstraction of Hardware Accelerators

• Published in: 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines pp. 170 - 177
• Main Authors: Ismail, A, Shannon, L
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2011
• Subjects: Acceleration; Context; Field programmable gate arrays; Fuses; Instruction sets; Kernel; Programming
• ISBN: 9781612842776; 1612842771
• DOI: 10.1109/FCCM.2011.48

SoCs can be implemented on a single FPGA, offering designers a unique opportunity for Embedded Systems. Instead of defining a fixed architecture early in the design process, the reconfigurable platform allows architectural redesign to meet the system's specific needs. However, the ability to instantiate new modules in the reconfigurable hardware provides a unique set of challenges for integration, particularly to the software (SW) designer. Specifically, the Operating System (OS) cannot automatically abstract these platform changes without redesign. In this paper, we present FUSE, a framework for HW accelerator abstraction that provides: 1) transparency to the SW designer at the application level, and 2) OS support for easy HW accelerator integration. We illustrate FUSE as an API for an embedded Linux OS with POSIX threads on Xilinx's Micro Blaze on a Virtex5. For three different applications and HW accelerators, we achieve performance speedups ranging from 6.4-37×.