HW/SW codesign incorporating edge delays using dynamic programming

We present an algorithm based on dynamic programming to perform the HW/SW partitioning and scheduling of a given task graph for minimum latency subject to resource constraint. The major contribution of this paper is to consider the edge communication delays in the dynamic programming solution of the...

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Bibliographic Details
Published in2003 Euromicro Symposium on Digital Systems Design (Euro-DSD 2003) pp. 264 - 271
Main Authors Bhasyam, K., Bazargan, K.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2003
Subjects
Costs
Data flow computing
Delay
Dynamic programming
Dynamic scheduling
Flow graphs
Heuristic algorithms
Partitioning algorithms
Runtime
Scheduling algorithm
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ISBN9780769520032
0769520030
DOI10.1109/DSD.2003.1231945

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Summary:We present an algorithm based on dynamic programming to perform the HW/SW partitioning and scheduling of a given task graph for minimum latency subject to resource constraint. The major contribution of this paper is to consider the edge communication delays in the dynamic programming solution of the problem. The algorithm has a polynomial run time complexity on trees. We also introduce a pruning technique to reduce the runtime of the worst-case scenario of directed acyclic graphs (DAGs). The algorithm has been implemented and the results are reported. A very fast quality heuristic is also proposed and implemented to provide good solutions in negligible run time.
ISBN:9780769520032
0769520030
DOI:10.1109/DSD.2003.1231945