Low resistive tungsten dual polymetal gate process for high speed and high density memory devices - Yong Soo Kim; Kwan-Yong Lim; Min-Gyu Sung; Soo-Hyun Kim; Hong-Seon Yang; Heung-Jae Cho; Se-Aug Jang; Jae-Geun Oh; Kwangok Kim; Young-Kyun Jung; Tae-Woo Jung; Choon-Hwan Kim; et al. (ESSDERC 2007 - 37th European Solid State Device Research Conference, 2007)
We developed ultra-low resistive tungsten dual polymetal gate memory device by using Ti-based diffusion barrier and a unique tungsten chemical vapor deposition (CVD) process with B 2 H 6 -based nucleation layer. The low resistive CVD-W (LRW) polymetal gate process not only reveals good gate oxide reliability comparable to PVD-W process, but also highly improved transistor performances such as signal delay characteristics.