Formal derivation of multilayered hardware/software structures

• Published in: ICFEM 2000 : Third IEEE International Conference on Formal Engineering Methods : York, England, September 4-6, 2000 pp. 5 - 13
• Main Author: Plaks, T.P.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2000
• Subjects: Algorithm design and analysis; Design methodology; Field programmable gate arrays; Hardware; Image processing; Parallel processing; Partitioning algorithms; Software algorithms; Software packages; Software tools
• ISBN: 9780769508221; 0769508227
• DOI: 10.1109/ICFEM.2000.873800

Presents a formal method for synthesising multi-layered regular processor arrays from algorithm specifications. A multi-layered array is a structure where 2D sub-arrays are connected into a 3D array only by one edge, and thus it fits, for example, the structure of a motherboard with FPGA daughter-boards. The synthesis of multi-layerd structures requires the extensive use of algebraic transformations, which is not possible using the classical regular array theory. We apply the iso-plane method which was developed for mapping reductions into regular arrays. In this paper, we further develop the iso-plane method and use it in a more general case - for decomposing a problem into parallel, loosely coupled parts (layered); we provide the conditions for regularly increasing the degree of parallelism in the problem specification; and we introduce partial lexicographic orders for data propagation and provide the conditions for mapping these data propagation structures on to arrays.