A novel CMOS charge-pump circuit with positive feedback for PLL applications

The design and simulation of a novel CMOS charge-pump circuit for PLL applications is presented. The proposed circuit makes use of positive feedback to increase the switching speed and current reuse to minimize the power consumption. H-SPICE simulations for a 0.35 /spl mu/m AMS technology show the p...

Full description

Saved in:
Bibliographic Details
Published in2001 8th International Conference on Electronics, Circuits and Systems Vol. 1; pp. 349 - 352 vol.1
Main Authors Juarez-Hernandez, E., Diaz-Sanchez, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2001
Subjects
Charge pumps
Circuit simulation
Energy consumption
Feedback circuits
Optical feedback
Phase frequency detector
Phase locked loops
Switches
Switching circuits
Voltage-controlled oscillators
Online AccessGet full text
ISBN9780780370579
0780370570
DOI10.1109/ICECS.2001.957751

Cover

More Information
Summary:The design and simulation of a novel CMOS charge-pump circuit for PLL applications is presented. The proposed circuit makes use of positive feedback to increase the switching speed and current reuse to minimize the power consumption. H-SPICE simulations for a 0.35 /spl mu/m AMS technology show the potential of the proposed structure for high-frequency applications.
ISBN:9780780370579
0780370570
DOI:10.1109/ICECS.2001.957751