Automated formal synthesis of Wallace Tree multipliers - Hasan, O.; Kort, S. (2007 50th Midwest Symposium on Circuits and Systems, 2007)
In this paper, we present a formal synthesis methodology that is capable of performing correct synthesis at almost all levels of abstraction and can be adapted to be used for most of the combinational digital circuits irrespective of their size and complexity. The proposed methodology calls for proving the correctness-preserving characteristic for the transformations that are required in the synthesis of a particular digital circuit in a higher-order-logic theorem prover. These correctness- preserving transformation proofs can then be used to automatically verify the correctness of the corresponding synthesis process within the theorem prover in an automated way. For illustration purposes, we present the construction of an automated formal synthesis tool for Wallace Tree multipliers based on our methodology.