A Reconfigurable Computing System Based on a Cache-Coherent Fabric

Typical reconfigurable computing systems are based on an I/O interconnect such as PCIe. This yields good bandwidth performance, but incurs significant overhead for small packet sizes, and makes the implementation of on-streaming-data applications unduly difficult. We describe an architecture based o...

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Bibliographic Details
Published in2011 International Conference on Reconfigurable Computing and FPGAs pp. 80 - 85
Main Authors Oliver, N., Sharma, R. R., Chang, S., Chitlur, B., Garcia, E., Grecco, J., Grier, A., Ijih, N., Yaping Liu, Marolia, P., Mitchel, H., Subhaschandra, S., Sheiman, A., Whisonant, T., Gupta, P.
Format Conference Proceeding
LanguageEnglish
Japanese
Published IEEE 01.11.2011
Subjects
cache coherent
Fabrics
Field programmable gate arrays
Hardware
in-socket FPGA
Kernel
Memory management
Protocols
Reconfigurable computing
shared virtual memory
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ISBN9781457717345
1457717344
ISSN2325-6532
DOI10.1109/ReConFig.2011.4

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Summary:Typical reconfigurable computing systems are based on an I/O interconnect such as PCIe. This yields good bandwidth performance, but incurs significant overhead for small packet sizes, and makes the implementation of on-streaming-data applications unduly difficult. We describe an architecture based on Intel ® Quick Path Interconnect ® that addresses these concerns.
ISBN:9781457717345
1457717344
ISSN:2325-6532
DOI:10.1109/ReConFig.2011.4