Design and implementation of efficient multiplier using Vedic mathematics - Rudagi, J.M; Ambli, V; Munavalli, V; Patil, R; Sajjan, V (3rd International Conference on Advances in Recent Technologies in Communication and Computing (ARTCom 2011), 2011)
Keywords: Digital arithmetic methods; Digital signal processing; Logic and switching circuits; Logic circuits; Signal processing and detection; real-time signal applications; multiplying circuits; DSP chip; signal processing; Multiply and Accumulate; fast multiplier circuit; key arithmetic operations; high speed multiplier; digital arithmetic; FFT; computation intensive arithmetic functions; microprocessors; vedic mathematics; filtering; digital signal processing; logic unit; signal processing applications; DSP algorithms; high speed processing; multiplier design; multiplication-based operations; DSP applications; MAC; fast Fourier transform; multiplication time; fundamental function; image processing applications; computer applications; multiplier implementation; instruction cycle time