Junctionless transistor: a review

• Published in: Proceedings of third International Conference on Computational Intelligence and Information Technology pp. 432 - 439
• Main Authors: Amin, S.I, Sarin, R.K
• Format: Conference Proceeding
• Language: English
• Published: Stevenage, UK IET 2013; The Institution of Engineering & Technology
• Subjects: Semiconductor device modelling, equivalent circuits, design and testing; subthreshold swing; transistors; nanoscale MOSFET device modelling; DIBL; short channel effect; nanowires; drain junction; junctionless transistor; uniformly doped nanowire; semiconductor device models; source junction; doping concentration gradient; oppositely doped substrate
• ISBN: 9781849198592; 1849198594
• DOI: 10.1049/cp.2013.2625

This paper is based on the extensive study of a Junctionless transistor. Since the entire conventional transistor have junction, which limits it's scaling as it requires very abrupt junction, high concentration gradient and become challenging with every technology node. The problems comes when there is a junction in such a device like MOSFETs which has source junction and drain junction formed with oppositely doped substrate. A junctionless transistor is a uniformly doped nanowire without junction and no doping concentration gradient exist. It shows better short channel effect and less degradation in mobility with temperature, small DIBL, subthreshold swing and higher voltage gain which shows good scalability below 10nm and reduces the fabrication complexity. Junctionless transistor is a very promising candidate for future nano scale MOSFET device.