Generic scrubbing-based architecture for custom error correction algorithms

• Published in: Proceedings (IEEE/IFIP International Symposium on Rapid System Prototyping. Online) pp. 112 - 118
• Main Authors: Santos, Rui, Venkataraman, Shyamsundar, Kumar, Akash
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01.10.2015
• Subjects: Algorithm design and analysis; Algorithms; Architecture; Architecture (computers); Computer architecture; Design analysis; Design engineering; Error correction; Error correction codes; Fault tolerance; Fault tolerant systems; Field programmable gate arrays; Hardware; Ports (Computers); Prototyping
• ISSN: 2150-5519
• DOI: 10.1109/RSP.2015.7416555

Scrubbing has been considered as an efficient mechanism to repair faults in the FPGA's configuration memory, when they are placed in harsh environments. By using this elementary mechanism, several academic solutions/algorithms based on error correction codes (ECCs) have been proposed. However, most of these proposed solutions are only theoretical and do not properly deal with the implementation concerns. With this paper we propose a generic scrubbing-based hardware architecture and design flow for implementing custom error correction algorithms based on ECCs. A conducted case study implementing and evaluating three different algorithms shows the feasibility and the efficiency of the proposed architecture and design flow.