Gate-level modelling of NBTI-induced delays under process variations - Copetti, Thiago; Medeiros, Guilherme; Bolzani Poehls, Leticia; Vargas, Fabian; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund (2016 17th Latin-American Test Symposium (LATS), 2016)
Keywords: aging; Computational modeling; Degradation; Delays; Integrated circuit modeling; Logic gates; MOSFET; NBTI; reliability; SPICE; static timing analysis