High performance VLSI adders

• Published in: 2015 3rd International Conference on Signal Processing, Communication and Networking (ICSCN) pp. 1 - 7
• Main Authors: Suganya, R., Meganathan, D.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2015
• Subjects: Adders; Algorithm design and analysis; Complexity theory; Computer architecture; Delays; Ling adder; Manchester carry chain adder; Signal processing algorithms; Very large scale integration; Weinberger adder
• DOI: 10.1109/ICSCN.2015.7219919

The objective of the work is to design and compare high performance and energy efficient VLSI adders for the various bit-level up to 64-bit using advanced CMOS technology. To compare the performance of the adders, recent algorithms of Weinberger, Ling and Manchester carry chain are selected amongst the high performance adders. These three algorithms are chosen because their efficient architectures make minimum dependency on bits over power, energy and delay than other VLSI adders. It has been observed that even though Manchester carry chain adder introduces more delay than other VLSI adders due to its chained architecture, it consumes less power due to its reduced transistor count. Weinberger adder has a parallel architecture with 2-bit conditional sum block that reduces the carry structure and overall computing delay compared to other high performance VLSI adders. Ling adder uses pseudo-carry which reduces number of logic stages compared to Weinberger adder. As a result of reduced logic stages, it takes least time to compute final carry compared to any other VLSI adders. The performance of the VLSI adders is compared based on power, energy consumption and delay. Advanced CMOS technology models (Predictive Technology Models) of 45nm, 32nm, 22nm and 16nm are used for simulation. HSPICE tool is used to simulate the performance of the VLSI adders.