A Metal-Only ECO Algorithm for Improving Hardware Security with Gate Camouflaging

Gate camouflaging is a useful method to protect integrated circuits from reverse engineering attacks. However, the design flow for the adoption of gate camouflaging has not been well studied. In this paper, we use camouflaged cells as spare cells. Then, a metal-only ECO (engineering change order) al...

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Published inIEEE International Conference on Consumer Electronics-China (Online) pp. 301 - 302
Main Authors Su, Liang-Ying, Huang, Shih-Hsu
Format Conference Proceeding
LanguageEnglish
Published IEEE 17.07.2023
Subjects
Consumer electronics
Hardware security
Integrated circuits
Logic gates
Resists
Reverse engineering
Reverse Engineering Attacks
Spare Cells
Timing
Timing Constraints
Online AccessGet full text
ISSN2575-8284
DOI10.1109/ICCE-Taiwan58799.2023.10226817

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Abstract Gate camouflaging is a useful method to protect integrated circuits from reverse engineering attacks. However, the design flow for the adoption of gate camouflaging has not been well studied. In this paper, we use camouflaged cells as spare cells. Then, a metal-only ECO (engineering change order) algorithm is proposed to maximize the hardware security by replacing normal cells with camouflaged cells under the same clock period constraint. Experiment results consistently show that the proposed ECO approach can effectively improve the hardware security without violating any timing constraint.
AbstractList Gate camouflaging is a useful method to protect integrated circuits from reverse engineering attacks. However, the design flow for the adoption of gate camouflaging has not been well studied. In this paper, we use camouflaged cells as spare cells. Then, a metal-only ECO (engineering change order) algorithm is proposed to maximize the hardware security by replacing normal cells with camouflaged cells under the same clock period constraint. Experiment results consistently show that the proposed ECO approach can effectively improve the hardware security without violating any timing constraint.
Author Su, Liang-Ying
Huang, Shih-Hsu
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  givenname: Shih-Hsu
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  email: shhuang@cycu.edu.tw
  organization: Chung Yuan Christian University,Department of Electronic Engineering,Taoyuan,Taiwan
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Snippet Gate camouflaging is a useful method to protect integrated circuits from reverse engineering attacks. However, the design flow for the adoption of gate...
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StartPage 301
SubjectTerms Consumer electronics
Hardware security
Integrated circuits
Logic gates
Resists
Reverse engineering
Reverse Engineering Attacks
Spare Cells
Timing
Timing Constraints
Title A Metal-Only ECO Algorithm for Improving Hardware Security with Gate Camouflaging
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