FPGA Based Adaptive Beamforming Using VSS LMS Algorithm

• Published in: 2024 IEEE 5th Women in Technology Conference (WINTECHCON) pp. 1 - 6
• Main Authors: Tittas, Nidhiya, G, Prabha
• Format: Conference Proceeding
• Language: English
• Published: IEEE 12.11.2024
• Subjects: Array signal processing; Basys 3; Convergence; Digital Beamforming; Field programmable gate arrays; FPGA; Hardware design languages; LMS; MATLAB; Pattern formation; Resource management; Signal to noise ratio; Software; Software algorithms; verilog; VSS
• DOI: 10.1109/Wintechcon61988.2024.10837941

The increased digitalization of the modern world has led to more frequent signal interferences, highlighting the need to separate the signal of interest from interfering signals. This is where digital beamforming becomes crucial. Digital beamforming using the Least Mean Square algorithm is a promising technique in this direction. However, the LMS approach has the drawback of increased delay for error convergence due to constant step size. When the step size is constant and the error is large it takes a lot of time to converge, similarly, when the step size is constant, and the error is small it results in overshooting and instability. Additionally, the constant step size LMS performs poorly with varying Signal to Noise Ratio. To address these issues, we propose a Variable Step Size LMS algorithm. The proposed VSS algorithm and existing CSS LMS algorithm were tested for error convergence and beam pattern formation using MATLAB software. The MATLAB simulations demonstrate that the Variable Step Size LMS algorithm outperforms the Constant Step Size LMS algorithm in terms of error convergence, beam pattern quality, and performance under varying SNR conditions. The proposed algorithm's architecture is designed and simulated in Vivado software on Basys 3 FPGA board using Verilog coding. Analysis and comparison is done in terms of resource utilization.