A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process

This paper describes an 11 b ADC realized using a 2.5 b pipelined stage followed by 9 b time interleaved SAR. Presented ADC designed in 65 nm CMOS process occupies 0.3 mm 2 area, achieves 59.1 dB SINAD at 100 Ms/s sampling frequency while dissipating 15 mW power from 1.2 V supply and resulting FOM i...

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Bibliographic Details
Published in2008 IEEE Custom Integrated Circuits Conference pp. 305 - 308
Main Authors Singh, P.N., Kumar, A., Debnath, C., Malik, R.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2008
Subjects
Bandwidth
Capacitors
CMOS process
Differential amplifiers
Driver circuits
Energy consumption
Frequency
MOSFETs
Sampling methods
Voltage
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ISBN9781424420186
1424420180
ISSN0886-5930
DOI10.1109/CICC.2008.4672082

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Summary:This paper describes an 11 b ADC realized using a 2.5 b pipelined stage followed by 9 b time interleaved SAR. Presented ADC designed in 65 nm CMOS process occupies 0.3 mm 2 area, achieves 59.1 dB SINAD at 100 Ms/s sampling frequency while dissipating 15 mW power from 1.2 V supply and resulting FOM is 0.20 pJ/step.
ISBN:9781424420186
1424420180
ISSN:0886-5930
DOI:10.1109/CICC.2008.4672082