A new systolic array algorithm for memory-based VLSI array implementation of DCT

• Published in: Computers and Communications: Proceedings of the IEEE Symposium on Computers and Communication, Alexandria, Egypt, 1997 pp. 297 - 301
• Main Author: Chiper, D.-F.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1997
• Subjects: Algorithm design and analysis; Concurrent computing; Convolution; Costs; Discrete cosine transforms; Hardware; Parallel processing; Signal processing algorithms; Systolic arrays; Very large scale integration
• ISBN: 9780818678523; 0818678526
• DOI: 10.1109/ISCC.1997.616015

A new approach for a memory-based VLSI realization of the 1D discrete cosine transform (1D-DCT) that significantly improves the previous designs is presented. This approach is based on a new formulation of an odd prime-length DCT algorithm. It uses two half-length cyclic convolutions with the same form, which are such reformulated that multipliers can be efficiently replaced by small biport ROMs and computed in parallel. Using this approach, high structural regularity, low hardware cost of the PE's and average computation time, and low I/O cost can be obtained. So, the average computation time has been reduced to one half and the throughput has been doubled, when compared with that of Guo et al. (1992). Thus an efficient systolic array for DCT, which is well suited for VLSI realization, can be obtained. It possesses also a much lower control complexity, it simpler interconnection structure, and a simpler hardware structure of the PEs, having thus a shorter cycle time. Moreover, it owns all other outstanding features of the VLSI array proposed by Guo et al.