CMOS/STT-MRAM Based Ascon LWC: a Power Efficient Hardware Implementation

• Published in: 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS) pp. 1 - 4
• Main Authors: Roussel, Nathan, Potin, Oliver, Di Pendina, Gregory, Dutertre, Jean-Max, Rigaud, Jean-Baptiste
• Format: Conference Proceeding
• Language: English
• Published: IEEE 24.10.2022
• Subjects: ASCON; Distance measurement; Hardware; Internet of Things; LWC; Microcontrollers; MTJ; NIST; non-volatile; Nonvolatile memory; Power demand; STT-MRAM
• DOI: 10.1109/ICECS202256217.2022.9971037

The increasing use of Internet of Things (IoT) objects is associated with a necessity to develop low-power and secure circuits. Lightweight Cryptography (LWC) algorithms are used to secure the communications of these connected objects at a limited power consumption. Energy harvesting techniques can provide the power required by IoT objects. However, it can be subject to sudden power loss, causing the system microcontroller to stop. To enable the cryptographic primitive to quickly recover from an unplanned power failure, we propose a CMOS/MRAM-based hardware implementation of the Asconcipher, a finalist of the National Institute of Standards and Technology (NIST) LWC contest. We focus on the ASIC design flow starting from an MTJ electrical model, without redeveloping the existing EDA tools. As case of study, an intermediate state of the Asconcomputations can be stored in the non-volatile memories and restored at startup after a power loss, saving the energy cost of a recalculation of the algorithm first steps. This implementation provides energy saving ranging from 11% to 48% for an area overhead of 5.5%.