Chapter 13 - Hardware Design and Realization for Iteratively Decodable Codes

• Published in: Channel Coding pp. 583 - 651
• Main Authors: Boutillon, Emmanuel, Masera, Guido
• Format: Book Chapter
• Language: English
• Published: Elsevier Ltd 2014
• Subjects: Analog circuits; ASIC; Belief propagation; Channel decoder; CMOS; Electronics; Engineering Sciences; Factor graphs; Flexible; FPGA; High throughput; Iterative decoding; LDPC decoder; Low power; Multi-standard; Signal and Image processing; Turbo decoder; VLSI decoder architectures; LDPC decoder; FPGA; Turbo decoder; Analog circuits; Low power; Iterative decoding; High throughput; CMOS; ASIC; Flexible; Channel decoder; Factor graphs; VLSI decoder architectures; Belief propagation; Multi-standard
• ISBN: 9780123964991; 012397223X; 0123964997; 9780123972231
• DOI: 10.1016/B978-0-12-396499-1.00013-3

The transition from analog telecommunication equipment and terminals to digital systems and, more recently, the fast development of wireless communications were made possible by three factors: 1) key advances in integrated circuit technology, 2) large improvements in methodologies and tools for the design of highly complex digital circuits, and 3) progress in information theory, in particular, the belief propagation algorithm that allows error control codes operating close to the Shannon limit. In this chapter, an overview of architecture of turbo and LDPC codes is presented. The standard implementation (i.e., low complexity) of those codes is first presented. Then architecture for high-speed, low-power, and high flexibility are derived. Finally, the chapter concludes with the presentation of exotic decoding architectures and a survey of relevant architectures.