A 38.1 fJ/bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation

• Published in: IEEE solid-state circuits letters p. 1
• Main Authors: Lee, Woojin, Sim, Changmin, Kim, Changjoo, Jeon, Jinwoo, Jung, Hyundo, Kim, Taihyun, Kim, Chulwoo
• Format: Journal Article
• Language: English
• Published: IEEE 09.09.2025
• Subjects: Capacitance; Capacitors; Clocks; coupling capacitor; Entropy; hardware security; Inverters; latch metastability; Latches; Logic gates; Mathematical models; Noise; Power demand; stochastic differential equation (SDE); true random number generator (TRNG)
• ISSN: 2573-9603; 2573-9603
• DOI: 10.1109/LSSC.2025.3608187

This work presents a capacitive-latch (C-latch) true random number generator (TRNG) that achieves both inverter mismatch autozeroing and accelerated evaluation by utilizing coupling capacitors. The proposed C-latch TRNG samples the mismatch between inverter equalization voltages through coupling capacitors during the equalization phase, effectively autozeroing inverter mismatch and enabling high-entropy raw bit generation without calibration. In addition, larger coupling capacitors reduce the effective capacitance in the gate-node stochastic differential equation, resulting in faster evaluation and reduced energy consumption. Fabricated in a 28-nm CMOS process, the TRNG achieves a minimum energy consumption of 38.1 fJ/bit at 0.4 V supply voltage and the maximum throughput of 162.48 Mb/s at 0.9 V. A 4-bit von Neumann post processor consistently extract a full entropy, which successfully passes all NIST SP800-22 and NIST SP800-90B randomness tests under wide voltage and temperature variations, implying both robustness and cryptographic suitability.