APA (7th ed.) Citation

Lee, W., Sim, C., Kim, C., Jeon, J., Jung, H., Kim, T., & Kim, C. (2025, September 9). A 38.1 fJ/bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation. IEEE solid-state circuits letters, 1. https://doi.org/10.1109/LSSC.2025.3608187

Chicago Style (17th ed.) Citation

Lee, Woojin, Changmin Sim, Changjoo Kim, Jinwoo Jeon, Hyundo Jung, Taihyun Kim, and Chulwoo Kim. "A 38.1 FJ/bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation." IEEE Solid-state Circuits Letters 9 Sep. 2025: 1. https://doi.org/10.1109/LSSC.2025.3608187.

MLA (9th ed.) Citation

Lee, Woojin, et al. "A 38.1 FJ/bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation." IEEE Solid-state Circuits Letters, 9 Sep. 2025, p. 1, https://doi.org/10.1109/LSSC.2025.3608187.