基于ECC校验码的存储器可扩展自修复算法设计
随着微电子工艺的不断进步，SoC芯片设计中SRAM所占面积越来越大，SRAM的缺陷率成为影响芯片成品率的重要因素。提出了一种可扩展的存储器自修复算法（S—MBISR），在对冗余的SRAM进行修复时，可扩展利用存储器访问通路中校验码的纠错能力，在不改变SRAM结构的前提下能够进一步提高存储器的容错能力，进而提高芯片成品率。最后对该算法进行了RTL设计实现。后端设计评估表明，该算法能够工作在1GHz频率，面积开销仅增加1．5％。...
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| Published in | 计算机工程与科学 Vol. 39; no. 2; pp. 252 - 257 |
|---|---|
| Main Author | |
| Format | Journal Article |
| Language | Chinese |
| Published |
江南计算技术研究所,江苏无锡,214083%数学工程与先进计算国家重点实验室,江苏无锡,214125
2017
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1007-130X |
| DOI | 10.3969/j.issn.1007-130X.2017.02.005 |
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| Abstract | 随着微电子工艺的不断进步，SoC芯片设计中SRAM所占面积越来越大，SRAM的缺陷率成为影响芯片成品率的重要因素。提出了一种可扩展的存储器自修复算法（S—MBISR），在对冗余的SRAM进行修复时，可扩展利用存储器访问通路中校验码的纠错能力，在不改变SRAM结构的前提下能够进一步提高存储器的容错能力，进而提高芯片成品率。最后对该算法进行了RTL设计实现。后端设计评估表明，该算法能够工作在1GHz频率，面积开销仅增加1．5％。 |
|---|---|
| AbstractList | 随着微电子工艺的不断进步，SoC芯片设计中SRAM所占面积越来越大，SRAM的缺陷率成为影响芯片成品率的重要因素。提出了一种可扩展的存储器自修复算法（S—MBISR），在对冗余的SRAM进行修复时，可扩展利用存储器访问通路中校验码的纠错能力，在不改变SRAM结构的前提下能够进一步提高存储器的容错能力，进而提高芯片成品率。最后对该算法进行了RTL设计实现。后端设计评估表明，该算法能够工作在1GHz频率，面积开销仅增加1．5％。 TP393; 随着微电子工艺的不断进步,SoC芯片设计中SRAM所占面积越来越大,SRAM的缺陷率成为影响芯片成品率的重要因素.提出了一种可扩展的存储器自修复算法(S-MBISR),在对冗余的SRAM进行修复时,可扩展利用存储器访问通路中校验码的纠错能力,在不改变SRAM结构的前提下能够进一步提高存储器的容错能力,进而提高芯片成品率.最后对该算法进行了RTL设计实现.后端设计评估表明,该算法能够工作在1 GHz频率,面积开销仅增加1.5％. |
| Abstract_FL | With the continuous progress of microelectronic technology,the static random access memory (SRAM) occupies the majority area of modern systems-on-a-chip (SoC),so the defect rate of the SRAM has become an important factor affecting the yield of chips.We propose a scalable memorybuilt-in-self-repair algorithm(S-MBISR)based on error checking and correcting (ECC) check code.With the same redundant SRAM structure,the correcting capability of the ECC code can enhance the fault tolerant capability,thus increasing the rate of finished product of chips effectively without increasing test time.We implement the algorithm on the RTL,and the evaluation of the back-end design shows that its working frequency can reach 1GHz while the area overhead is only 1.5％. |
| Author | 任秀江 谢向辉 施晶晶 |
| AuthorAffiliation | 江南计算技术研究所,江苏无锡214083 数学工程与先进计算国家重点实验室,江苏无锡214125 |
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| Author_FL | REN Xiu-jiang XIE Xiang-hui SHI Jing-jing |
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| Copyright | Copyright © Wanfang Data Co. Ltd. All Rights Reserved. |
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| Notes | REN Xiu-jiang1 ,XIE Xiang-hui2 ,SHI Jing-jingl （1. J iangnan Institute of Computing Technology, Wuxi 214083; 2. State Key Laboratory of Mathematical Engineering and Advanced Computing,Wuxi 214125 ,China） 43-1258/TP With the continuous progress of microelectronic technology, the static random access memory （SRAM） occupies the majority area of modern systems-on-a-chip （SoC）, so the defect rate of the SRAM has become an important factor affecting the yield of chips. We propose a scalable memorybuilt-in-self-repair algorithm（S-MBISR）based on error checking and correcting （ECC） check code. With the same redundant SRAM structure, the correcting capability of the ECC code can enhance the faulttolerant capability, thus increasing the rate of finished product of chips effectively without increasing test time. We implement the algorithm on the RTL, and the evaluation of the back-end design shows that its working frequency can reach 1GHz while the area overhead is only 1.5 %. MBSIR ; MBIST ; ECC |
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| Publisher | 江南计算技术研究所,江苏无锡,214083%数学工程与先进计算国家重点实验室,江苏无锡,214125 |
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| Snippet | 随着微电子工艺的不断进步，SoC芯片设计中SRAM所占面积越来越大，SRAM的缺陷率成为影响芯片成品率的重要因素。提出了一种可扩展的存储器自修复算法（S—MBISR），在对冗余... TP393; 随着微电子工艺的不断进步,SoC芯片设计中SRAM所占面积越来越大,SRAM的缺陷率成为影响芯片成品率的重要因素.提出了一种可扩展的存储器自修复算法(S-MBISR),在对冗余... |
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| Title | 基于ECC校验码的存储器可扩展自修复算法设计 |
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