LHC光纤数据链路传输中LOCic系统编解码延时测量

在高速数据传输中,数据传输延时是表征编解码系统性能的重要参数,特别是在欧洲核子中心LHC（大型强子对撞机）ATLAS（超环面仪器实验）探测器读出系统里尤为重要.针对将用于LHC ATLAS实验升级中的LOCic（线码在芯片专用集成电路）线性编码系统的FPGA实现给出了其延时参数测量的设计方法和实现过程.准确地测得了延时大小,说明了LOCic线性编码的低延时特性,为用于ATLAS实验升级中对该线性编码系统性能标定提供了依据....

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Published in	电子技术应用 Vol. 41; no. 6; pp. 69 - 72
Main Author	邓彬伟刘天宽
Format	Journal Article
Language	Chinese
Published	南方卫理公会大学物理系,德克萨斯州达拉斯75275%南方卫理公会大学物理系,德克萨斯州达拉斯75275 2015 湖北理工学院,电气与电子信息工程学院,湖北黄石435003
Subjects	ATLAS实验升级 LOCic 大型强子对撞机延时测量高速数据传输 high-speed data transmission 延时测量 ATLAS实验升级大型强子对撞机 latency measurement LHC 高速数据传输 ATLAS phase-1 LOCic
Online Access	Get full text
ISSN	0258-7998
DOI	10.16157/j.issn.0258-7998.2015.06.019

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Abstract	在高速数据传输中,数据传输延时是表征编解码系统性能的重要参数,特别是在欧洲核子中心LHC（大型强子对撞机）ATLAS（超环面仪器实验）探测器读出系统里尤为重要.针对将用于LHC ATLAS实验升级中的LOCic（线码在芯片专用集成电路）线性编码系统的FPGA实现给出了其延时参数测量的设计方法和实现过程.准确地测得了延时大小,说明了LOCic线性编码的低延时特性,为用于ATLAS实验升级中对该线性编码系统性能标定提供了依据.
AbstractList	在高速数据传输中,数据传输延时是表征编解码系统性能的重要参数,特别是在欧洲核子中心LHC（大型强子对撞机）ATLAS（超环面仪器实验）探测器读出系统里尤为重要.针对将用于LHC ATLAS实验升级中的LOCic（线码在芯片专用集成电路）线性编码系统的FPGA实现给出了其延时参数测量的设计方法和实现过程.准确地测得了延时大小,说明了LOCic线性编码的低延时特性,为用于ATLAS实验升级中对该线性编码系统性能标定提供了依据. TP206+.1; 在高速数据传输中,数据传输延时是表征编解码系统性能的重要参数,特别是在欧洲核子中心LHC(大型强子对撞机)ATLAS(超环面仪器实验)探测器读出系统里尤为重要.针对将用于LHC ATLAS实验升级中的LOCic(线码在芯片专用集成电路)线性编码系统的FPGA实现给出了其延时参数测量的设计方法和实现过程.准确地测得了延时大小,说明了LOCic线性编码的低延时特性,为用于ATLAS实验升级中对该线性编码系统性能标定提供了依据.
Author	邓彬伟刘天宽
AuthorAffiliation	湖北理工学院,电气与电子信息工程学院,湖北黄石435003 南方卫理公会大学物理系,德克萨斯州达拉斯75275
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Author_FL	Liu Tiankuan Deng Binwei
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DocumentTitleAlternate	Latency measurement of LOCic for the optical data links of LHC experiments
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Keywords	high-speed data transmission 延时测量 ATLAS实验升级大型强子对撞机 latency measurement LHC 高速数据传输 ATLAS phase-1 LOCic
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Notes	Deng Binwei, Liu Tiankuan（1.School of Electric and Electronic Information Engineering ,Hubei Polytechnic University, Huangshi 435003, China; 2.Department of Physics, Sothern Methodist University, Dallas 75275 ,USA） high-speed data transmission ; latency measurement ; LOCic ; LHC ; ATLAS phase- 1 11-2305/TN In high-speed data transmission, data transmission latency is one of the important parameters of characterization of encoding and decoding system performance. Especially, in the CERN＇s the large hadron collider（LHC） ATLAS detector readout sys- tem shorter latency is particularly important. As for the LOCic （line of code in application-specific integrated circuit chip） which will be applied to the LHC ATLAS experiment upgrade, the FPGA firmware of the linear coding system has given the designing methods and the implementation process for the time delay parameters test. According to this way, it has measured the size of de- lay accurately, and has illustrated the low-latency characteristics of linear code of the
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SubjectTerms	ATLAS实验升级 LOCic 大型强子对撞机延时测量高速数据传输
Title	LHC光纤数据链路传输中LOCic系统编解码延时测量
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