一种基于MDAC优化的低功耗流水线A／D转换器
设计了一种低功耗16位100MS／s的流水线A／D转换器。通过采用级间电容缩减技术，并优化增益数模转换器（MDAC）的结构，降低采样电容的面积。流水线前两级采用高性能低功耗运算跨导放大器（OTA），通过动态偏置技术进一步降低功耗。芯片采用0．18μm混合信号CMOS工艺，1．8V单电源供电。经测试，流水线A／D转换器在5MHz的输入频率下，信噪失真比（SNDR）为74．2dB，无杂散动态范围（SFDR）为91．9dB，整体功耗为210mW。...
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| Published in | 电子技术应用 Vol. 43; no. 1; pp. 68 - 71 |
|---|---|
| Main Author | |
| Format | Journal Article |
| Language | Chinese |
| Published |
北京微电子技术研究所,北京,100076
2017
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| Subjects | |
| Online Access | Get full text |
| ISSN | 0258-7998 |
| DOI | 10.16157/j.issn.0258-7998.2017.01.018 |
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| Abstract | 设计了一种低功耗16位100MS／s的流水线A／D转换器。通过采用级间电容缩减技术，并优化增益数模转换器（MDAC）的结构，降低采样电容的面积。流水线前两级采用高性能低功耗运算跨导放大器（OTA），通过动态偏置技术进一步降低功耗。芯片采用0．18μm混合信号CMOS工艺，1．8V单电源供电。经测试，流水线A／D转换器在5MHz的输入频率下，信噪失真比（SNDR）为74．2dB，无杂散动态范围（SFDR）为91．9dB，整体功耗为210mW。 |
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| AbstractList | TN47; 设计了一种低功耗16位100 MS/s的流水线A/D转换器.通过采用级间电容缩减技术,并优化增益数模转换器(MDAC)的结构,降低采样电容的面积.流水线前两级采用高性能低功耗运算跨导放大器(OTA),通过动态偏置技术进一步降低功耗.芯片采用0.18 μm混合信号CMOS工艺,1.8 V单电源供电.经测试,流水线A/D转换器在5 MHz的输入频率下,信噪失真比(SNDR)为74.2 dB,无杂散动态范围(SFDR)为91.9 dB,整体功耗为210 mW. 设计了一种低功耗16位100MS／s的流水线A／D转换器。通过采用级间电容缩减技术，并优化增益数模转换器（MDAC）的结构，降低采样电容的面积。流水线前两级采用高性能低功耗运算跨导放大器（OTA），通过动态偏置技术进一步降低功耗。芯片采用0．18μm混合信号CMOS工艺，1．8V单电源供电。经测试，流水线A／D转换器在5MHz的输入频率下，信噪失真比（SNDR）为74．2dB，无杂散动态范围（SFDR）为91．9dB，整体功耗为210mW。 |
| Author | 杨龙 王宗民 |
| AuthorAffiliation | 北京微电子技术研究所,北京100076 |
| AuthorAffiliation_xml | – name: 北京微电子技术研究所,北京,100076 |
| Author_FL | Wang Zongmin Yang Long |
| Author_FL_xml | – sequence: 1 fullname: Yang Long – sequence: 2 fullname: Wang Zongmin |
| Author_xml | – sequence: 1 fullname: 杨龙 王宗民 |
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| ClassificationCodes | TN47 |
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| Copyright | Copyright © Wanfang Data Co. Ltd. All Rights Reserved. |
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| DOI | 10.16157/j.issn.0258-7998.2017.01.018 |
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| DocumentTitleAlternate | A low power pipelined ADC with improved MDAC |
| DocumentTitle_FL | A low power pipelined ADC with improved MDAC |
| EndPage | 71 |
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| Keywords | dynamic biasing 功耗OTA low power OTA pipelined ADC MDAC 动态偏置 流水线A/D转换器 |
| Language | Chinese |
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| Notes | low power OTA ; MDAC ; dynamic biasing ; pipelined ADC The design of a low power 16-bit 100 MS/s pipelined analog-to-digital converter（ADC） is presented in this paper. The area of sampling capacitor and the chip is reduced by adopting stage scaling technology and optimizing the structure of multiply dig- ital-to-analog converter（MDAC）. Low power dissipation and high performance operational trans-conductance amplifiers（OTA） in the first two pipelined stages are realized by using dynamic biasing technology. This work is implemented in 0.18μm mixture signal CMOS process with a 1.8 V power supply. The pipelined ADC exhibits 91.9 dB SFDR and 74.2 dB SNDR, consuming 210 mW with 5 MHz differential input signal. Yang Long,Wang Zongmin （Beijing Microelectronics Tech. Institution, Beijing 100076, China） 11-2305/TN |
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| Snippet | 设计了一种低功耗16位100MS／s的流水线A／D转换器。通过采用级间电容缩减技术，并优化增益数模转换器（MDAC）的结构，降低采样电容的面积。流水线前两级采用高性能低功耗运... TN47; 设计了一种低功耗16位100 MS/s的流水线A/D转换器.通过采用级间电容缩减技术,并优化增益数模转换器(MDAC)的结构,降低采样电容的面积.流水线前两级采用高性能低功耗运... |
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| SubjectTerms | MDAC 功耗OTA 动态偏置 流水线A／D转换器 |
| Title | 一种基于MDAC优化的低功耗流水线A／D转换器 |
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