Hybrid 2D–CMOS microchips for memristive applications

• Published in: Nature (London) Vol. 618; no. 7963; pp. 57 - 62
• Main Authors: Zhu, Kaichen, Pazos, Sebastian, Aguirre, Fernando, Shen, Yaqing, Yuan, Yue, Zheng, Wenwen, Alharbi, Osamah, Villena, Marco A., Fang, Bin, Li, Xinyi, Milozzi, Alessandro, Farronato, Matteo, Muñoz-Rojo, Miguel, Wang, Tao, Li, Ren, Fariborzi, Hossein, Roldan, Juan B., Benstetter, Guenther, Zhang, Xixiang, Alshareef, Husam N., Grasser, Tibor, Wu, Huaqiang, Ielmini, Daniele, Lanza, Mario
• Format: Journal Article
• Language: English
• Published: London Nature Publishing Group UK 01.06.2023; Nature Publishing Group
• Subjects: 639/166/987; 639/301/357/1018; Alternation learning; Boron; Boron nitride; Circuits; CMOS; Computation; Density; Electrodes; Electronic circuits; Electrons; Fabrication; Firing pattern; Graphene; Humanities and Social Sciences; Integrated circuits; Integration; Interconnections; Logic circuits; Memristors; Monolayers; multidisciplinary; Multilayers; Neural networks; Pinholes; Science; Science (multidisciplinary); Semiconductors; Silicon; Silicon dioxide; Silicon substrates; Silicon wafers; Technology assessment; Transistors; Two dimensional materials
• ISSN: 0028-0836; 1476-4687; 1476-4687
• DOI: 10.1038/s41586-023-05973-1

Exploiting the excellent electronic properties of two-dimensional (2D) materials to fabricate advanced electronic circuits is a major goal for the semiconductor industry 1 , 2 . However, most studies in this field have been limited to the fabrication and characterization of isolated large (more than 1 µm 2 ) devices on unfunctional SiO 2 –Si substrates. Some studies have integrated monolayer graphene on silicon microchips as a large-area (more than 500 µm 2 ) interconnection 3 and as a channel of large transistors (roughly 16.5 µm 2 ) (refs.  4 , 5 ), but in all cases the integration density was low, no computation was demonstrated and manipulating monolayer 2D materials was challenging because native pinholes and cracks during transfer increase variability and reduce yield. Here, we present the fabrication of high-integration-density 2D–CMOS hybrid microchips for memristive applications—CMOS stands for complementary metal–oxide–semiconductor. We transfer a sheet of multilayer hexagonal boron nitride onto the back-end-of-line interconnections of silicon microchips containing CMOS transistors of the 180 nm node, and finalize the circuits by patterning the top electrodes and interconnections. The CMOS transistors provide outstanding control over the currents across the hexagonal boron nitride memristors, which allows us to achieve endurances of roughly 5 million cycles in memristors as small as 0.053 µm 2 . We demonstrate in-memory computation by constructing logic gates, and measure spike-timing dependent plasticity signals that are suitable for the implementation of spiking neural networks. The high performance and the relatively-high technology readiness level achieved represent a notable advance towards the integration of 2D materials in microelectronic products and memristive applications. High-integration-density 2D–CMOS hybrid microchips for memristive applications are made demonstrating in-memory computation and electrical response suitable for the implementation of spiking neural networks representing an advance towards integration of 2D materials in microelectronic products and memristive applications.