A compute-in-memory chip based on resistive random-access memory

• Published in: Nature (London) Vol. 608; no. 7923; pp. 504 - 512
• Main Authors: Wan, Weier, Kubendran, Rajkumar, Schaefer, Clemens, Eryilmaz, Sukru Burc, Zhang, Wenqiang, Wu, Dabin, Deiss, Stephen, Raina, Priyanka, Qian, He, Gao, Bin, Joshi, Siddharth, Wu, Huaqiang, Wong, H.-S. Philip, Cauwenberghs, Gert
• Format: Journal Article
• Language: English
• Published: London Nature Publishing Group UK 18.08.2022; Nature Publishing Group
• Subjects: 142/126; 639/166/987; 639/705/117; 639/925/927/1007; Accuracy; Algorithms; Artificial intelligence; Bayesian analysis; Chips (memory devices); Circuit design; Circuits; CMOS; Computer applications; Design; Design optimization; Energy efficiency; Flexibility; Hardware; Hierarchies; Humanities and Social Sciences; Image classification; Image processing; Image reconstruction; Mathematical analysis; Mathematical models; Modelling; multidisciplinary; Neurons; Object recognition; Optimization techniques; Random access memory; Science; Science (multidisciplinary); Semiconductors; Software; Speech recognition; Versatility
• ISSN: 0028-0836; 1476-4687; 1476-4687
• DOI: 10.1038/s41586-022-04992-8

Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM) 1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory 2 – 5 . Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware 6 – 17 , it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM—a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST 18 and 85.7 percent on CIFAR-10 19 image classification, 84.7-percent accuracy on Google speech command recognition 20 , and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task. A compute-in-memory neural-network inference accelerator based on resistive random-access memory simultaneously improves energy efficiency, flexibility and accuracy compared with existing hardware by co-optimizing across all hierarchies of the design.