A compute-in-memory chip based on resistive random-access memory

Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM) 1 promises to meet such demand by storing AI model weights in dense,...

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Published in	Nature (London) Vol. 608; no. 7923; pp. 504 - 512
Main Authors	Wan, Weier, Kubendran, Rajkumar, Schaefer, Clemens, Eryilmaz, Sukru Burc, Zhang, Wenqiang, Wu, Dabin, Deiss, Stephen, Raina, Priyanka, Qian, He, Gao, Bin, Joshi, Siddharth, Wu, Huaqiang, Wong, H.-S. Philip, Cauwenberghs, Gert
Format	Journal Article
Language	English
Published	London Nature Publishing Group UK 18.08.2022 Nature Publishing Group
Subjects	142/126 639/166/987 639/705/117 639/925/927/1007 Accuracy Algorithms Artificial intelligence Bayesian analysis Chips (memory devices) Circuit design Circuits CMOS Computer applications Design Design optimization Energy efficiency Flexibility Hardware Hierarchies Humanities and Social Sciences Image classification Image processing Image reconstruction Mathematical analysis Mathematical models Modelling multidisciplinary Neurons Object recognition Optimization techniques Random access memory Science Science (multidisciplinary) Semiconductors Software Speech recognition Versatility
Online Access	Get full text
ISSN	0028-0836 1476-4687 1476-4687
DOI	10.1038/s41586-022-04992-8

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Abstract	Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM) 1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory 2 – 5 . Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware 6 – 17 , it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM—a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST 18 and 85.7 percent on CIFAR-10 19 image classification, 84.7-percent accuracy on Google speech command recognition 20 , and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task. A compute-in-memory neural-network inference accelerator based on resistive random-access memory simultaneously improves energy efficiency, flexibility and accuracy compared with existing hardware by co-optimizing across all hierarchies of the design.
AbstractList	Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM) 1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory 2 – 5 . Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware 6 – 17 , it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM—a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST 18 and 85.7 percent on CIFAR-10 19 image classification, 84.7-percent accuracy on Google speech command recognition 20 , and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task. A compute-in-memory neural-network inference accelerator based on resistive random-access memory simultaneously improves energy efficiency, flexibility and accuracy compared with existing hardware by co-optimizing across all hierarchies of the design. Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM)1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory2-5. Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware6-17, it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM-a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST18 and 85.7 percent on CIFAR-1019 image classification, 84.7-percent accuracy on Google speech command recognition20, and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task.Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM)1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory2-5. Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware6-17, it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM-a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST18 and 85.7 percent on CIFAR-1019 image classification, 84.7-percent accuracy on Google speech command recognition20, and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task. Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM) promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory. Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware, it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM-a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST and 85.7 percent on CIFAR-10 image classification, 84.7-percent accuracy on Google speech command recognition, and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task. Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM) 1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory 2–5 . Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware 6–17 , it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM—a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST 18 and 85.7 percent on CIFAR-10 19 image classification, 84.7-percent accuracy on Google speech command recognition 20 , and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task. Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM) promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory . Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware , it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM-a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST and 85.7 percent on CIFAR-10 image classification, 84.7-percent accuracy on Google speech command recognition , and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task.
Author	Qian, He Kubendran, Rajkumar Zhang, Wenqiang Schaefer, Clemens Wong, H.-S. Philip Gao, Bin Wu, Huaqiang Eryilmaz, Sukru Burc Raina, Priyanka Wan, Weier Cauwenberghs, Gert Wu, Dabin Deiss, Stephen Joshi, Siddharth
Author_xml	– sequence: 1 givenname: Weier orcidid: 0000-0003-3507-9014 surname: Wan fullname: Wan, Weier email: weierwan@stanford.edu organization: Stanford University, University of California San Diego – sequence: 2 givenname: Rajkumar orcidid: 0000-0003-3066-4898 surname: Kubendran fullname: Kubendran, Rajkumar organization: University of California San Diego, University of Pittsburgh – sequence: 3 givenname: Clemens surname: Schaefer fullname: Schaefer, Clemens organization: University of Notre Dame – sequence: 4 givenname: Sukru Burc surname: Eryilmaz fullname: Eryilmaz, Sukru Burc organization: Stanford University – sequence: 5 givenname: Wenqiang surname: Zhang fullname: Zhang, Wenqiang organization: Tsinghua University – sequence: 6 givenname: Dabin surname: Wu fullname: Wu, Dabin organization: Tsinghua University – sequence: 7 givenname: Stephen surname: Deiss fullname: Deiss, Stephen organization: University of California San Diego – sequence: 8 givenname: Priyanka surname: Raina fullname: Raina, Priyanka organization: Stanford University – sequence: 9 givenname: He surname: Qian fullname: Qian, He organization: Tsinghua University – sequence: 10 givenname: Bin orcidid: 0000-0002-2417-983X surname: Gao fullname: Gao, Bin email: gaob1@tsinghua.edu.cn organization: Tsinghua University – sequence: 11 givenname: Siddharth surname: Joshi fullname: Joshi, Siddharth email: sjoshi2@nd.edu organization: University of California San Diego, University of Notre Dame – sequence: 12 givenname: Huaqiang surname: Wu fullname: Wu, Huaqiang email: wuhq@tsinghua.edu.cn organization: Tsinghua University – sequence: 13 givenname: H.-S. Philip surname: Wong fullname: Wong, H.-S. Philip email: hspwong@stanford.edu organization: Stanford University – sequence: 14 givenname: Gert orcidid: 0000-0002-3166-5529 surname: Cauwenberghs fullname: Cauwenberghs, Gert email: gert@ucsd.edu organization: University of California San Diego
BackLink	https://www.ncbi.nlm.nih.gov/pubmed/35978128$$D View this record in MEDLINE/PubMed
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Snippet	Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge...
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SubjectTerms	142/126 639/166/987 639/705/117 639/925/927/1007 Accuracy Algorithms Artificial intelligence Bayesian analysis Chips (memory devices) Circuit design Circuits CMOS Computer applications Design Design optimization Energy efficiency Flexibility Hardware Hierarchies Humanities and Social Sciences Image classification Image processing Image reconstruction Mathematical analysis Mathematical models Modelling multidisciplinary Neurons Object recognition Optimization techniques Random access memory Science Science (multidisciplinary) Semiconductors Software Speech recognition Versatility
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Title	A compute-in-memory chip based on resistive random-access memory
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