A New Fault Tolerant Routing Algorithm for Networks on Chip
To provide correct data transmission and to handle the communication requirements, the routing algorithm should find a new path to steer packets from the source to the destination in a faulty network. Many solutions have been proposed to overcome faults in network-on-chips (NoCs). This article intro...
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| Published in | International journal of embedded and real-time communication systems Vol. 10; no. 3; pp. 68 - 85 |
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| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
Hershey
IGI Global
01.07.2019
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1947-3176 1947-3184 |
| DOI | 10.4018/IJERTCS.2019070105 |
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| Abstract | To provide correct data transmission and to handle the communication requirements, the routing algorithm should find a new path to steer packets from the source to the destination in a faulty network. Many solutions have been proposed to overcome faults in network-on-chips (NoCs). This article introduces a new fault-tolerant routing algorithm, to tolerate permanent and transient faults in NoCs. This solution called DINRA can satisfy simultaneously congestion avoidance and fault tolerance. In this work, a novel approach inspired by Catnap is proposed for NoCs using local and global congestion detection mechanisms with a hierarchical sub-network architecture. The evaluation (on reliability, latency and throughput) shows the effectiveness of this approach to improve the NoC performances compared to state of art. In addition, with the test module and fault register integrated in the basic architecture, the routers are able to detect faults dynamically and re-route packets to fault-free and congestion-free zones. |
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| AbstractList | To provide correct data transmission and to handle the communication requirements, the routing algorithm should find a new path to steer packets from the source to the destination in a faulty network. Many solutions have been proposed to overcome faults in network-on-chips (NoCs). This article introduces a new fault-tolerant routing algorithm, to tolerate permanent and transient faults in NoCs. This solution called DINRA can satisfy simultaneously congestion avoidance and fault tolerance. In this work, a novel approach inspired by Catnap is proposed for NoCs using local and global congestion detection mechanisms with a hierarchical sub-network architecture. The evaluation (on reliability, latency and throughput) shows the effectiveness of this approach to improve the NoC performances compared to state of art. In addition, with the test module and fault register integrated in the basic architecture, the routers are able to detect faults dynamically and re-route packets to fault-free and congestion-free zones. |
| Author | Nehnouh, Chakib Senouci, Mohamed |
| AuthorAffiliation | University of Oran1 Ahmed Ben Bella, Oran, Algeria |
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| Cites_doi | 10.1109/PDP.2013.75 10.1109/TPDS.2016.2588482 10.1109/ASPDAC.2013.6509555 10.1109/IOLTS.2015.7229835 10.1109/SiPS.2013.6674530 10.1016/j.micpro.2014.04.003 10.1145/2508148.2485950 10.1145/146628.140384 10.1109/TCAD.2011.2181509 10.1109/DSD.2012.82 10.1109/TC.2015.2425887 10.1145/2886781 10.1109/ISCAS.2014.6865545 10.1109/TPDS.2016.2521641 10.1145/1391469.1391584 10.1109/PACT.2011.61 10.1109/NCA.2010.14 10.1109/DSD.2013.42 10.1145/1629911.1630119 10.7873/DATE.2013.324 10.1007/978-1-4614-8274-1_8 10.1049/iet-cdt.2012.0054 10.1109/ISCAS.2015.7168945 10.1145/2522968.2522976 10.1109/NoCS.2013.6558401 |
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| Copyright | Copyright © 2019, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited. |
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| SubjectTerms | Algorithms Communication Congestion Data transmission Energy consumption Failure Fault detection Fault tolerance Faults Hierarchies Network latency Packets (communication) Reliability analysis Routers Semiconductors System on chip |
| Title | A New Fault Tolerant Routing Algorithm for Networks on Chip |
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