A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm

• Published in: IEEE journal of solid-state circuits Vol. 42; no. 2; pp. 361 - 373
• Main Authors: Yang, Rong-Jyi, Liu, Shen-Iuan
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.02.2007; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Added delay; ADDLL; Algorithms; Applied sciences; Approximation; Approximation algorithms; Balancing; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); Clocks; CMOS; CMOS technology; Counting circuits; DCC; Delay lines; delay-locked loop (DLL); Design. Technologies. Operation analysis. Testing; edge combine; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Frequency; Hardware; harmonic lock; Integrated circuits; Jitter; Mathematical analysis; Registers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; successive approximation register (SAR); Synchronous; variable successive approximation register (VSAR); Harmonic; successive approximation register (SAR); Closed loop; delay-locked loop (DLL); edge combine; variable successive approximation register (VSAR); DCC; Jitter; Clock; Algorithm; Combiner circuit; Successive approximation; ADDLL; Complementary MOS technology; harmonic lock; Delay lock loops; Low-power electronics; Root mean square value
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2006.889381

A wide-range all-digital delay-locked loop (ADDLL) is presented to achieve low jitter, low power and process immunity. The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation. It can also achieve the fast-locking property and closed-loop operation. With the balanced edge combiner, the ADDLL outputs a synchronous clock with the duty cycle close to 50% when the duty cycle of the input clock varies from 20% to 80%. Fabricated in 0.18mum CMOS technology, the ADDLL maintains a fixed one input clock cycle latency from 40MHz to 550MHz without the harmonic-locking issue. It dissipates 12.6mW from a 1.8V supply at 550 MHz. The measured root-mean-square and peak-to-peak jitters at 550MHz are 1.5ps and 12ps, respectively