Efficient FPGA Implementation of Multilayer Perceptron for Real-Time Human Activity Classification

• Published in: IEEE access Vol. 7; pp. 26696 - 26706
• Main Authors: Gaikwad, Nikhil B., Tiwari, Varun, Keskar, Avinash, Shivaprakash, N. C.
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accuracy; Activity recognition; Algorithms; Classification; classifier hardware implementation; Computer architecture; Datasets; Entropy (Information theory); field programmable gate array; Field programmable gate arrays; Hardware; Human activity recognition; Mathematical model; Moving object recognition; multilayer perceptron; Multilayer perceptrons; Parallel processing; Performance evaluation; Power consumption; Real-time systems; Resource utilization; smart military wearables; Smart phones; Topology
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2019.2900084

The smartphone-based human activity recognition (HAR) systems are not capable to deliver high-end performance for challenging applications. We propose a dedicated hardware-based HAR system for smart military wearables, which uses a multilayer perceptron (MLP) algorithm to perform activity classification. To achieve the flexible and efficient hardware design, the inherent MLP architecture with parallel computation is implemented on FPGA. The system performance has been evaluated using the UCI human activity dataset with 7767 feature samples of 20 subjects. The three combinations of a dataset are trained, validated, and tested on ten different MLP models with distinct topologies. The MLP design with the 7-6-5 topology is finalized from the classification accuracy and cross entropy performance. The five versions of the final MLP design (7-6-5) with different data precision are implemented on FPGA. The analysis shows that the MLP designed with 16-bit fixed-point data precision is the most efficient MLP implementation in the context of classification accuracy, resource utilization, and power consumption. The proposed MLP design requires only 270 ns for classification and consumes 120 mW of power. The recognition accuracy and hardware results performance achieved are better than many of the recently reported works.