FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability
Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7and 10-nm...
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          | Published in | IEEE journal of the Electron Devices Society Vol. 6; pp. 332 - 340 | 
|---|---|
| Main Authors | , , , , , | 
| Format | Journal Article | 
| Language | English | 
| Published | 
        New York
          IEEE
    
        01.01.2018
     The Institute of Electrical and Electronics Engineers, Inc. (IEEE)  | 
| Subjects | |
| Online Access | Get full text | 
| ISSN | 2168-6734 2168-6734  | 
| DOI | 10.1109/JEDS.2018.2804383 | 
Cover
| Abstract | Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7-nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10-nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the subthreshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7-nm FinFET than that for the 10-nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6-nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred (110) channel orientation is more resilient to the MGG and LER variability in both architectures. | 
    
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| AbstractList | Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7-nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10-nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the subthreshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7-nm FinFET than that for the 10-nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6-nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred (110) channel orientation is more resilient to the MGG and LER variability in both architectures. | 
    
| Author | Kalna, Karol Seoane, Natalia Nagy, Daniel Garcia-Loureiro, Antonio J. Elmessary, Muhammad A. Indalecio, Guillermo  | 
    
| Author_xml | – sequence: 1 givenname: Daniel orcidid: 0000-0003-0854-6596 surname: Nagy fullname: Nagy, Daniel email: daniel.nagy@usc.es organization: Centro Singular de Investigación en Tecnoloxías da Información, University of Santiago de Compostela, Santiago de Compostela, Spain – sequence: 2 givenname: Guillermo orcidid: 0000-0001-7727-1704 surname: Indalecio fullname: Indalecio, Guillermo organization: Centro Singular de Investigación en Tecnoloxías da Información, University of Santiago de Compostela, Santiago de Compostela, Spain – sequence: 3 givenname: Antonio J. orcidid: 0000-0003-0574-1513 surname: Garcia-Loureiro fullname: Garcia-Loureiro, Antonio J. organization: Centro Singular de Investigación en Tecnoloxías da Información, University of Santiago de Compostela, Santiago de Compostela, Spain – sequence: 4 givenname: Muhammad A. orcidid: 0000-0001-9732-9010 surname: Elmessary fullname: Elmessary, Muhammad A. organization: Nanoelectronic Devices Computational Group, Swansea University, Swansea, U.K – sequence: 5 givenname: Karol orcidid: 0000-0002-6333-9189 surname: Kalna fullname: Kalna, Karol organization: Nanoelectronic Devices Computational Group, Swansea University, Swansea, U.K – sequence: 6 givenname: Natalia orcidid: 0000-0003-0973-461X surname: Seoane fullname: Seoane, Natalia organization: Centro Singular de Investigación en Tecnoloxías da Información, University of Santiago de Compostela, Santiago de Compostela, Spain  | 
    
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| Snippet | Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D... | 
    
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| SubjectTerms | Computer simulation density gradient (DG) quantum corrections Drift-diffusion (DD) FinFETs Gallium arsenide gate-all-around (GAA) nanowire (NW) FET line edge roughness (LER) Logic gates metal grain granularity (MGG) Metals Monte Carlo (MC) simulations Nanoscale devices Nanowires Schrödinger equation based quantum corrections Semiconductor process modeling Si FinFET Silicon  | 
    
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| Title | FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability | 
    
| URI | https://ieeexplore.ieee.org/document/8288601 https://www.proquest.com/docview/2299131532 https://doi.org/10.1109/jeds.2018.2804383 https://doaj.org/article/edf10bca70f14f7dbb5c1f513b0fb80b  | 
    
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