FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7and 10-nm...

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Published inIEEE journal of the Electron Devices Society Vol. 6; pp. 332 - 340
Main Authors Nagy, Daniel, Indalecio, Guillermo, Garcia-Loureiro, Antonio J., Elmessary, Muhammad A., Kalna, Karol, Seoane, Natalia
Format Journal Article
LanguageEnglish
Published New York IEEE 01.01.2018
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Online AccessGet full text
ISSN2168-6734
2168-6734
DOI10.1109/JEDS.2018.2804383

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Abstract Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7-nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10-nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the subthreshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7-nm FinFET than that for the 10-nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6-nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred (110) channel orientation is more resilient to the MGG and LER variability in both architectures.
AbstractList Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7-nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10-nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the subthreshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7-nm FinFET than that for the 10-nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6-nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred (110) channel orientation is more resilient to the MGG and LER variability in both architectures.
Author Kalna, Karol
Seoane, Natalia
Nagy, Daniel
Garcia-Loureiro, Antonio J.
Elmessary, Muhammad A.
Indalecio, Guillermo
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Snippet Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D...
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SubjectTerms Computer simulation
density gradient (DG) quantum corrections
Drift-diffusion (DD)
FinFETs
Gallium arsenide
gate-all-around (GAA) nanowire (NW) FET
line edge roughness (LER)
Logic gates
metal grain granularity (MGG)
Metals
Monte Carlo (MC) simulations
Nanoscale devices
Nanowires
Schrödinger equation based quantum corrections
Semiconductor process modeling
Si FinFET
Silicon
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Title FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability
URI https://ieeexplore.ieee.org/document/8288601
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https://doi.org/10.1109/jeds.2018.2804383
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