Dataflow object detection system for FPGA-based smart camera

• Published in: IET circuits, devices & systems Vol. 10; no. 4; pp. 280 - 291
• Main Authors: Bourrasset, Cédric, Maggiani, Luca, Sérot, Jocelyn, Berry, François
• Format: Journal Article
• Language: English
• Published: Stevenage The Institution of Engineering and Technology 01.07.2016; John Wiley & Sons, Inc; Institution of Engineering and Technology
• Subjects: Algorithms; Cameras; CAPH programming language; Classification; communication protocols; Computation; Computer Science; Computer vision; Computer Vision and Pattern Recognition; configurable object detection; data flow analysis; dataflow object detection system; Digital imaging; digital video frame rates; distributed algorithms; Electronics; embedded computer vision; Engineering Sciences; Field programmable gate arrays; flexible smart cameras; FPGA-based smart camera; generated code; Handwriting; Hardware description languages; hardware descriptions; high level dataflow specifications; high resolution image sensors; Histograms; Image resolution; image sensors; linear SVM-based classification; massive data parallelism; Mathematical models; object detection; Object recognition; on-board processing; oriented gradients; Platforms; Programming languages; Real time; real-time processing constraints; real-time systems; real-time vision processing; Sensor arrays; Sensors; Smart sensors; smart vision systems; support vector machines; Video communication; Vision systems; real-time vision processing; digital video frame rates; field programmable gate arrays; high resolution image sensors; object detection; programming languages; generated code; cameras; high level dataflow specifications; real-time processing constraints; linear SVM-based classification; FPGA-based smart camera; on-board processing; embedded computer vision; support vector machines; CAPH programming language; data flow analysis; communication protocols; massive data parallelism; dataflow object detection system; image sensors; oriented gradients; hardware descriptions; configurable object detection; distributed algorithms; real-time systems; computer vision; smart vision systems; flexible smart cameras
• ISSN: 1751-858X; 1751-8598; 1751-8598
• DOI: 10.1049/iet-cds.2015.0071

Embedded computer vision based smart systems raise challenging issues in many research fields, including real-time vision processing, communication protocols or distributed algorithms. The amount of data generated by cameras using high resolution image sensors requires powerful computing systems to be processed at digital video frame rates. Consequently, the design of efficient and flexible smart cameras, with on-board processing capabilities, has become a key issue for the expansion of smart vision systems relying on decentralised processing at the image sensor node level. In this context, field programmable gate arrays (FPGA)-based platforms, supporting massive data parallelism, offer large opportunities to match real-time processing constraints compared with platforms based on general purpose processors. In this study, the authors describe the implementation, on such a platform, of a configurable object detection application, reformulated according to the dataflow model of computation. The application relies on the computation of the histogram of oriented gradients and a linear SVM-based classification. It is described using the CAPH programming language, allowing efficient hardware descriptions to be generated automatically from high level dataflow specifications without prior knowledge of hardware description languages such as VHDL or Verilog. Results show that the performance of the generated code does not suffer from a significant overhead compared with handwritten HDL code.