Systolic array architecture implementing Berlekamp-Massey-Sakata algorithm for decoding codes on a class of algebraic curves

• Published in: IEEE transactions on information theory Vol. 51; no. 11; pp. 3856 - 3871
• Main Authors: Matsui, H., Sakata, S., Kurihara, M., Mita, S.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.11.2005; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algebra; Algorithms; Applied sciences; Arrays; Berlekamp-Massey-Sakata (BMS) algorithm; Circuits; Codes; codes on algebraic curves; Coding, codes; Construction; Equations; Errors; Exact sciences and technology; Galois fields; GrÖbner basis; High speed; Information, signal and communications theory; Iterative algorithms; Iterative decoding; Joints; Logic; Materials science and technology; parallel decoding; Polynomials; Signal and communications theory; systolic array; Systolic arrays; Telecommunications and information theory; Two dimensional displays; Access control; Gröbner basis; codes on algebraic curves; Majority logic; Network architecture; Algebraic code; Berlekamp Massey algorithm; Two dimensional model; Decoding; Systolic network; Implementation; Locator; parallel decoding; Multiscale method; systolic array; Minimal distance; Error correction; Berlekamp-Massey-Sakata (BMS) algorithm
• ISSN: 0018-9448; 1557-9654
• DOI: 10.1109/TIT.2005.856950

We construct a two-dimensional systolic array implementing the Berlekamp-Massey-Sakata (BMS) algorithm to provide error-locator polynomials for codes on selected algebraic curves. This array is constructed by introducing some new polynomials in order to increase the parallelism of the algorithm. The introduced polynomials are used in the majority logic scheme by Sakata et al. to correct errors up to the designed minimum distance without affecting its high speed. The arrangement of the nearest local connection of processing units in the systolic array is obtained for the general case. Furthermore, shortened systolic arrays that reduce the circuit scale and have the same function are constructed with only a slight modification of the connections and controls; this enables the adjustment of the circuit scale for different types of systems.