Device optimization for digital subthreshold logic operation

• Published in: IEEE transactions on electron devices Vol. 52; no. 2; pp. 237 - 247
• Main Authors: Paul, B.C., Raychowdhury, A., Roy, K.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.02.2005; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Circuit optimization; Circuit properties; CMOS integrated circuits; Delay; Design; Design. Technologies. Operation analysis. Testing; Device optimization; Devices; Digital circuits; Display; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Electronics industry; Exact sciences and technology; Integrated circuits; Logic; Logic circuits; MOSFETs; Semiconductor device modeling; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; subthreshold operation; Threshold voltage; Transistors; ultralow power applications; Performance evaluation; Inverter; Voltage threshold; MOSFET; Plasma display panel; Logic design; Optimization; ultralow power applications; Logic circuit; subthreshold operation; Power consumption; Device optimization; Energy dissipation; Complementary MOS technology; Digital circuit; Delay time; CMOS integrated circuits; Low-power electronics; Threshold logic; Flat panel displays
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2004.842538

Digital circuits operated in the subthreshold region (supply voltage less than the transistor threshold voltage) can have orders of magnitude power advantage over standard CMOS circuits for applications requiring ultralow power and medium frequency of operation. Although the implication of technology scaling on subthreshold operation is not obvious (since an obsolete technology node can deliver the same performance as a scaled technology in subthreshold), it has been shown that technology scaling helps to reduce the supply-voltage and, hence, the power consumption at iso-performance. It is possible to implement subthreshold logic circuits using the standard transistors that are designed primarily for ultra high performance super-threshold logic design. However, an Si MOSFET so optimized for performance in the super-threshold regime is not the best device to use in the subthreshold domain. We propose device designs apt for subthreshold operation. Results show that the optimized device improves the delay and power delay product (PDP) of an inverter chain by 44% and 51%, respectively, over the normal super-threshold device operated in the subthreshold region.