A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures - Hagio, Yuta; Yanagisawa, Masao; Togawa, Nozomu (IPSJ Transactions on System LSI Design Methodology, 2014)
Keywords: Algorithms; Binding; Delay; distributed-register architecture; High level synthesis; Level (quantity); post-silicon tuning; process and delay variation; Scheduling