FPGA and ASIC realisation of EMD algorithm for real-time signal processing - Das, Kaushik; Nath, Debanjali; Pradhan, Sambhu Nath (IET circuits, devices & systems, 2020)
Keywords: Algorithms; application specific integrated circuit; Application specific integrated circuits; ASIC; Cadence Genus tool; Cadence Innovus tool; clock gating; Design; Digilentinc Basys 3 FPGA board; Digital signal processors; dynamic power reduction; EMD algorithm; empirical mode decomposition algorithm; Field programmable gate arrays; field‐programmable gate array; frequency 25.0 MHz; hardware description languages; hardware verification; Hilbert transforms; integrated circuit design; interpolation; Layouts; logic design; mathematics computing; Modules; moving average; power consumption reduction; Power management; real‐time signal processing; Research Article; sawtooth transform; semiconductor laboratory cell library; Signal processing; simulation phase; size 180.0 nm; smoothing module; Software; splines (mathematics); traditional cubic spline interpolation; Verilog‐HDL code; Xilinx Vivado; splines (mathematics); real-time signal processing; field programmable gate arrays; signal processing; mathematics computing; Digilentinc Basys 3 FPGA board; hardware description languages; Verilog-HDL code; field-programmable gate array; Cadence Innovus tool; moving average; Hilbert transforms; semiconductor laboratory cell library; ASIC; integrated circuit design; application specific integrated circuit; dynamic power reduction; smoothing module; sawtooth transform; empirical mode decomposition algorithm; clock gating; size 180.0 nm; Xilinx Vivado; simulation phase; interpolation; Cadence Genus tool; frequency 25.0 MHz; EMD algorithm; power consumption reduction; traditional cubic spline interpolation; hardware verification; application specific integrated circuits; logic design